Infineon implemented on-chip debug
support (OCDS) some years ago for its own
16-bit and 32-bit architectures. In addition to
reading and writing main memory while the
program is running, OCDS enables code breakpoints
in flash and data breakpoints. Even the
continuous monitoring of a memory location
without specific trace hardware is possible
thanks to a special trigger transfer mechanism.
For more demanding requirements, the concept
is enhanced with so-called emulation devices.
These are special devices that are only available
for debug and test purposes. In addition to
the production chip, the emulation devices
contain on-chip trace memory as well as
sophisticated trigger and filter logic.
With its XMC4000 family (XMC stands for
cross-market microcontroller), Infineon now
also offers microcontrollers based on the ARM
Cortex-M4 processor core for a broad range
of industrial applications. Besides a large number
of communication interfaces (such as CAN,
Ethernet, USB, etc), human machine interface
(HMI) and powerful peripherals for signal
generation, control and processing, the new
XMC4000 industrial microcontrollers also feature
a new on-chip debug concept.
It is well-known today that ARM offers a large
number of licensable controller cores, which,
if required, can be completed by the licensees
with their own peripherals to full SoCs. Less
well known on the other hand is that under
the name CoreSight, ARM also offers a wide
range of diverse, scalable technologies for debugging
and testing its processors. The most
interesting thing about this IP building block
is that since no compelling relationship exists
between the core and debug features, every licensed
semiconductor manufacturer can freely
choose which functions it implements and
which not. The technologies offered under
CoreSight cover a wide range of test functionalities.
These range from simple target access
via JTAG with run control and trace with low
bandwidth, through to high-end trace with
high frequencies and large amounts of data.
Figure 3 shows a simplified block diagram of
the CoreSight components used with the new
XMC4000 family. On-chip debug functions,
in accordance with state-of-the-art technology
nowadays, are provided via a JTAG debug port
(J-DP) with five signal lines or the more recent
serial wire debug port (SW-DP) interface with
two signal lines. This combination is called
SWJ-DP. Furthermore, with the serial wire
viewer (SWV), trace functionality with low
bandwidth is also available to the developer.
The viewer gives out trace information via a
single pin. On the one hand, the instrumentation
trace macrocell (ITM), and on the other
hand, the data watchpoint and trace unit
(DWT), serve as information sources. The
DWT contains a statistic counter for completed
cycles, sleep cycles, the interrupt load, the average
number of cycles per instruction and
the number of certain instruction types. The
counters generate a trace message per overflow.
This information can be utilized for optimization
of the application performance. Furthermore,
the DWT contains logic functions, with
the help of which changes to program variables
can be recognized, a trace message generated
or the instruction counter cyclically outputted.
The application software can even generate
trace events by description of ITM registers
(printf style debugging). However, a complete
reconstruction of the program flow is not
possible with the characteristics described.
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